Principal Staff Dft Engineer Idc - - Microchip Technology
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Microchip is the leading provider of embedded semiconductor products and one of the key enablers for IoT solutions. Microchip Wireless Solutions Group (WSG) is looking for Staff SoC DFT Engineer to support SOC development for our next generation WiFi/Bluetooth MIPS/ARM based controller targeted for wider range of applications in IoT and embedded space.
Must have prior DFT leadership experience in handling large complex SoC/ASICs and should have handled at least one SoC tapeout from start to finish. Should have hands-on experience in ATPG, MBIST and repair, LBIST, JTAG (IEEE 1149.1), scan compression, fault models and fault simulations, ATPG coverage improvements and simulation with timing, at-speed testing, transition and path delay ATPG, Pre and post DFT insertion Formal, gate level simulations.
Exposure to DFT techniques for analog/mixed-signal/RF would be desirable. Candidates with limited/no exposure to analog/RF should be willing to learn in longer term.
Excellent debugging skills – scan failures/blockage, DFT DRC failures, timing (setup/hold) failures, signature analysis
Expertise in industry standard EDA tools for test such as Mentor Tessent suite, Synopsys DFT compiler
Scripting skills in Perl, Tcl, System Verilog
Excellent communication and analytical skills
Experience in working with sites located in different parts of the world.
Successful candidate will Lead all DFT tasks of large wireless SoCs for the WSG group.
Work closely with design and backend team and define/improve DFT methodology for SoCs Will be responsible for full-chip SCAN, ATPG, Boundary Scan, MBIST, LBIST etc.
Signoff on DRC and other DFT verification checks. Silicon bringup and post silicon debug/diagnosis with close cooperation with Design and Yield.
Should have working knowledge on manufacturing test systems. Must be able to handle aggressive but realistic tapeout plans and crunch time situations.
Expertise in RTL coding using Verilog/SystemVerilog
Knowledgeable in Chip level Design and Integration activities
Hands on Experience with C Programming Language
Proficiency in common UNIX scripting languages (Perl, Python, csh, etc.)
Excellent debug skills in both functional and gate level simulations
Good Knowledge of SOC peripherals like ADC/Timers/ECAN/USB/Ethernet
Knowledge of revision control tools such as CVS, Perforce, DesignSync
Working knowledge of semiconductor device physics, transistor characteristics, and associated layout considerations
Solid Written and Verbal Communication skills
Experience working with cross functional global teams
Clear history of task ownership and proactively addressing issues
9 to 15 years of experience in DFT Engineering
Expert knowledge of DFT architecture on complex SoCs with multiple power and clock domains.
Experience with standard JTAG protocol and Boundary scan.
Experience in ATPG flows – pattern generation, simulation and bring-up.
Expert knowledge on Coverage improvement and Test time reduction.
Exposure to Logic synthesis, Logic Equivalence, Scan insertion methodologies and Test Timing closure.
Experience in DFT related RTL integration.
Experience in industry standard DFT tools - Mentor Tessent suite, Synopsys DFT compiler.
Experience in Low-Power DFT requirements.
Experience in DFT related RTL integration and exposure to verification of DFx features at RTL/Gate level.
Experience in functional vector generation for coverage improvements and for Characterization is a plus.
Experience in Gate and RTL simulations for functional pattern generation using C/Assembly infrastructure is a plus.
Experience of working with Teradyne tester.
Structural silicon debug and timing and yield improvements on large chips.
Exposure to Design for validation/debug strategies.
BS or MS in Electrical/Electronic Engineering with 9+ years experience, MSEE preferred