18 Mar

Verification Engineer - Hyderabad - Microsemi

Position
Verification Engineer
Company
Microsemi
Location
Hyderabad AP
Opening
18 Mar, 2017 30+ days ago

Microsemi as the company that open the jobs vacancy, have some qualification and spesification especially for the Verification Engineer jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Microsemi company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.

Should be experienced working on Pre silicon Verification on complex SOCs, including block level / chip level full test bench design, development using constrained random styled Testbench architectures. Responsibilities also include, but are not limited to, architecting complex reusable Test benches, development and implementation of TLM based verification environments using concepts of OOPs/HVL's, test plan development, test suite development, functional coverage models and plans, debug, assertions, monitors / checkers, PERL/TCL, Scripting and DFT.Should have architected and designed constrained random styled Test benches using Systemverilog and OVM/UVM, targeted for reusability with or without using Testbench Methodologies. Required Qualifications: * Should have 3 to 5 years of experience in verification.* Hands on working experience in SV/OVM/UVM based constrained random styled TLM based verification environments.* Must have prior experience working with SOC based verification environments at block, unit and top level testbenches.* Strong academics with specialization in VLSI technology and digital technology.* Must possess exceptional interpersonal, analytical, and communications skills.* Able to work in a challenging and engaging environment that promotes teamwork, creativity, accountability, and professional development.* Should have worked in multisite team culture with teams spread across the world.* Good in scripting using languages like Perl, TCL, and Makefiles etc. Preferred Qualifications: * Experience with Ethernet, IP and Telecom networks.* Prior Knowledge and experience in HVL's like System Verilog, Open Vera, 'e' language.* Good in Verilog HDL / VHDL languages to understand and read the designs.* Exposure to advanced verification methodologies like UVM, AVM, VMM, URM, RVM or eRM etc. Bachelor's degree in Engineering required. Master's degree preferred. Degree from a local reputed university would be preferred. Vitesse offers a competitive salary and comprehensive benefits package. We are an equal opportunity employer EEO/M/F/D/V.

Preferred Qualifications: * Experience with Ethernet, IP and Telecom networks.* Prior Knowledge and experience in HVL's like System Verilog, Open Vera, 'e' language.* Good in Verilog HDL / VHDL languages to understand and read the designs.* Exposure to advanced verification methodologies like UVM, AVM, VMM, URM, RVM or eRM etc. Bachelor's degree in Engineering required. Master's degree preferred. Degree from a local reputed university would be preferred. Vitesse offers a competitive salary and comprehensive benefits package. We are an equal opportunity employer EEO/M/F/D/V.


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